• DocumentCode
    886162
  • Title

    Design of parity testable combinational circuits

  • Author

    Bhattacharya, Bhargab B. ; Seth, Sharad C.

  • Author_Institution
    Indian Stat. Inst., Calcutta, India
  • Volume
    38
  • Issue
    11
  • fYear
    1989
  • fDate
    11/1/1989 12:00:00 AM
  • Firstpage
    1580
  • Lastpage
    1584
  • Abstract
    The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin are required to complete the design. The test procedure is simple, and the hardware overhead is low
  • Keywords
    combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; design for testability; maximal supergates; parity testable combinational circuits; single external test-mode pin; Circuit analysis; Circuit testing; Combinational circuits; Computer science; Design for testability; Feeds; Hardware; Logic circuits; Logic design; Logic testing;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.42129
  • Filename
    42129
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=886162