Title :
Design of parity testable combinational circuits
Author :
Bhattacharya, Bhargab B. ; Seth, Sharad C.
Author_Institution :
Indian Stat. Inst., Calcutta, India
fDate :
11/1/1989 12:00:00 AM
Abstract :
The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin are required to complete the design. The test procedure is simple, and the hardware overhead is low
Keywords :
combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; design for testability; maximal supergates; parity testable combinational circuits; single external test-mode pin; Circuit analysis; Circuit testing; Combinational circuits; Computer science; Design for testability; Feeds; Hardware; Logic circuits; Logic design; Logic testing;
Journal_Title :
Computers, IEEE Transactions on
