Title :
Unidirectional systolic multiplier
Author :
Ait-Boudaoud, D.
Author_Institution :
Bournmouth Univ., Poole, UK
Abstract :
A high throughput unidirectional systolic multiplier is presented. The new architecture is based on the cell merging approach, where each basic building unit is a radix-2 bit-level cell. A comparison with the existing pipelined multiplier shows that the proposed architecture reduces the latency by at least 40%.
Keywords :
digital arithmetic; multiplying circuits; systolic arrays; architecture; cell merging; high throughput; latency-reduction; parallel architecture; radix-2 bit-level cell; unidirectional systolic multiplier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19921211
