A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Author

Miyawaki, Yoshikazu ; Nakayama, Takeshi ; Kobayashi, Shin-ichi ; Ajika, Natsuo ; Ohi, Makoto ; Terada, Yasushi ; Arima, Hideaki ; Yoshihara, Tsutomu

Author_Institution

Mutsubishi Electr. Corp., Hyogo, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

583

Lastpage

588

Abstract

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories

Keywords

CMOS integrated circuits; EPROM; VLSI; integrated memory circuits; 16 Mbit; 5 V; 5-V-only erase operations; 64 Mbit; CMOS; EEPROM; Fowler-Nordheim tunneling; VLSI; chip size penalty; circuit technologies; clamp scheme; erasing scheme; flash memories; flash programming scheme; low supply voltage operation; low supply voltage read operations; negative gate biased erasing scheme; programming before erasure; row decoding scheme; word-line boost; Channel hot electron injection; Circuits; Clamps; Decoding; EPROM; Flash memory; Handheld computers; Low voltage; Threshold voltage; Tunneling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126547

Filename

126547