Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM´s

Author

Kawahara, Takayuki ; Kawajiri, Yoshiki ; Kitsukawa, Goro ; Sagara, Kazuhiko ; Kawamoto, Yoshifumi ; Akiba, Takesada ; Kato, Shisei ; Kawase, Yasushi ; Itoh, Kiyoo

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

589

Lastpage

596

Abstract

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design

Keywords

BIMOS integrated circuits; DRAM chips; VLSI; 0.3 micron; 10 ns; 4 Mbit; BiCMOS; BiCMOS output circuit; DRAMs; ECL; MOS preamplifier; MOS transistor parameter control; VLSI; bipolar main amplifier; circuit technology; ease of design; layout area; reliability; sensing scheme; BiCMOS integrated circuits; Driver circuits; Helium; High power amplifiers; Laboratories; MOSFETs; Operational amplifiers; Preamplifiers; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126548

Filename

126548