DocumentCode
886486
Title
A Synthesis of Combinational Logic with NAND or NOR Elements
Author
Ellis, D.T.
Author_Institution
Electronic Data Processing Div., Applied Research Dept., Honeywell, Inc., Needham, Mass.
Issue
5
fYear
1965
Firstpage
701
Lastpage
705
Abstract
A synthesis technique is developed which forms an all NAND or all NOR structure from a combinational logical expression. The resultant structure has a maximum of three logic levels. It is shown that the structure can be obtained directly from the prime implicants describing the logical expression. Also, by grouping prime implicants into any one of three basic patterns, a reduction in the size of the structure can be realized. The paper uses the NAND element to develop the synthesis technique, and then extends the technique to include NOR synthesis.
Keywords
Delay effects; Digital integrated circuits; Helium; Inspection; Integrated circuit synthesis; Inverters; Logic; Signal design; Signal generators; Signal synthesis;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1965.264209
Filename
4038555
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