1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

Author

Ning, Tak H. ; Cook, P.W. ; Dennard, R.H. ; Osburn, C.M. ; Schuster, S.E.

Volume

14

Issue

2

fYear

1979

fDate

4/1/1979 12:00:00 AM

Firstpage

268

Lastpage

275

Abstract

For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.

Keywords

Field effect integrated circuits; Hot carriers; Integrated logic circuits; Large scale integration; Logic design; field effect integrated circuits; hot carriers; integrated logic circuits; large scale integration; logic design; Current measurement; Information geometry; Leakage current; MOSFET circuits; Silicon; Stress measurement; Substrate hot electron injection; Temperature; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1979.1051173

Filename

1051173