Scaling I/sup 2/L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.