An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit

Author

Sato, T. ; Sakate, M. ; Okada, H. ; Sukemura, T. ; Goto, G.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

657

Lastpage

659

Abstract

The authors discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented. It uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than for conventional carry select adders. The adder is integrated into an area of 0.41×3.36 mm² achieved by a 0.8-μm, triple-metal, full-CMOS process

Keywords

CMOS integrated circuits; adders; digital arithmetic; integrated logic circuits; 0.8 micron; 8.5 ns; carry-skip paths; conditional sum generation circuit; conflict-free bypass circuit; control scheme; full-CMOS process; mutually exclusive transmission gates; propagation delay time; transmission gate adder; triple-metal; Adders; CMOS process; Circuits; Control systems; Delay estimation; Floating-point arithmetic; Propagation delay; Signal design; Signal generators; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126557

Filename

126557