A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Author

Ohuchi, M. ; Okamura, T. ; Sawairi, A. ; Kuniba, F. ; Matsumoto, K. ; Tashiro, T. ; Hatakeyama, S. ; Okuyama, K.

Author_Institution

NEC Corp., Kawasaki, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

664

Lastpage

667

Abstract

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f_max), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding

Keywords

bipolar integrated circuits; elemental semiconductors; emitter-coupled logic; integrated logic circuits; large scale integration; multiplexing equipment; optical communication equipment; silicon; 4.2 Gbit/s; 5 Gbit/s; ECL termination; RF grounding; Si; bipolar technology; chip capacitors; chip resistors; demultiplexer; digital optical links; multigigabit LSIs; multiplexer; package design technology; parasitic capacitance modeling; six-layer ceramic package; switching current optimization; Capacitors; Ceramics; Design optimization; Frequency; MESFETs; Multiplexing; Packaging; Parasitic capacitance; Resistors; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126559

Filename

126559