DocumentCode
886884
Title
A 1.7-V adjustable I/O interface for low-voltage fast SRAMs
Author
Ishibashi, Koichiro ; Sasaki, Katsuro ; Yamanaka, Toshiaki ; Toyoshima, Hiroshi ; Kojima, Fumio
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
27
Issue
4
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
674
Lastpage
677
Abstract
An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V
Keywords
CMOS integrated circuits; SRAM chips; buffer circuits; convertors; -3.6 V; 1.7 V; 4.3 ns; 64 kbit; CMOS SRAM; ECL; TTL; access time; adjustable I/O interface; all-CMOS output buffer; fast static RAM; low-voltage; output buffer; reduced swing level; source-follower circuit; voltage-follower; wired-OR connection; Availability; Delay; Differential amplifiers; Driver circuits; Feedback loop; Hot carriers; MOSFET circuits; Mirrors; Random access memory; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.126562
Filename
126562
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