Validation of Latch-Up Mitigation in Complex VLSI Circuits

FXR testing, circuit simulation, and computer automated design rule checks (DRCs) have been performed to validate the mitigation techniques used for latch-up protection of non-epi TRW devices. Innovative modification of DRC software has been specially adapted to perform exhaustive search for latch sensitive structures. These are used to pinpoint locations where critical spacings may violate circuit safeguards intended to prevent triggering n-p-n-p four layer structures in a gamma dot event. Sample data is given to illustrate the validation flow from circuit modeling of latch sensitive regions, to automated layout analysis, and finally, state vector selection with LINAC and FXR results using a bit error rate (BER) exerciser.