DocumentCode :
887130
Title :
Static and dynamic noise margins of logic circuits
Author :
Lohstroh, Jan
Volume :
14
Issue :
3
fYear :
1979
fDate :
6/1/1979 12:00:00 AM
Firstpage :
591
Lastpage :
598
Abstract :
Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example.
Keywords :
Electron device noise; Integrated logic circuits; electron device noise; integrated logic circuits; Boundary conditions; Circuit noise; Computer simulation; Flip-flops; Impedance; Integrated circuit measurements; Logic circuits; Noise level; Noise measurement; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1979.1051221
Filename :
1051221
Link To Document :
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