Title :
Comparison of various binary dividers in I/sup 2/L and CHIL technology
Author :
Ablassmeier, Ulrich
fDate :
6/1/1979 12:00:00 AM
Abstract :
The conventional six-gate I/SUP 2/L binary divider and some four-gate dividers were built and compared. The six-gate divider requires the most real estate, but its design presents no critical problems; it has the highest maximum divider frequency and the smallest power dissipation per input switching operation.
Keywords :
Dividing circuits; Frequency dividers; Integrated logic circuits; dividing circuits; frequency dividers; integrated logic circuits; Assembly; Conductivity; Epitaxial layers; Flip-flops; Frequency conversion; Integrated circuit interconnections; Performance evaluation; Power dissipation; Substrates; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1979.1051235
