A preemptive scheduling mechanism for accurate behavioral simulation of digital designs

The authors examine the limitations of the timing semantics in the conventional behavioral simulators and present a preemptive scheduling mechanism for accurate behavioral simulation results. They consider two signal transitions at the input ports of a component, where the second input transition arrives later than the first transition. The first and second input transitions cause first output signal transitions O₁ and O₂, respectively, to be generated at the output port of the component. When the logical values of O₁ and O₂ conflict with each other and O₁ arrives later than O₂ , O₁ is preempted by O₂. In addition, an input signal to a component whose pulse duration is smaller than the inertial delay of the component, T_mip , is discarded during simulation. Empirical measures for T_mip relative to the high-to-low and low-to-high propagation delays of the component for TL (transistor-transistor logic), NMOS, and CMOS technologies are presented. This approach has been implemented in the ADLIB-SABLE simulator at Stanford University