On the logic delay in MOS LSI static NOR designs

Conventional definitions of logic block delay are reviewed and a preferred one is proposed, on a statistical basis, for the static NOR circuits in an LSI MOSFET technology. According to this definition, the delay is based on the actual circuit thresholds depends minimally on the input transition rate and is always positive. Moreover critical pulsewidths are given directly in terms of block delays. Using this definition, the block and path delay statistics are derived for use in CAD simulation of chip logic and performance in some limited sense. Finally, examples are given illustrating the use of delay definition in chip delay and pulsewidth.