Title :
Low-frequency noise considerations for MOS amplifiers design
Author :
Bertails, Jean-Claude
fDate :
8/1/1979 12:00:00 AM
Abstract :
Equivalent input noise voltages of MOS amplifiers working in a low-frequency range have been calculated in the three basic technologies, i.e., single-channel enhancement-load, single-channel depletion-load and CMOS. Means of reducing that noise are discussed and practical results given for CMOS technology.
Keywords :
Differential amplifiers; Field effect integrated circuits; Linear integrated circuits; Noise; differential amplifiers; field effect integrated circuits; linear integrated circuits; noise; 1f noise; Bipolar transistors; CMOS technology; Circuit noise; Low-frequency noise; Low-noise amplifiers; Noise reduction; Semiconductor device noise; Solid state circuit design; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1979.1051262
