• DocumentCode
    887557
  • Title

    Time Loss Through Gating of Asynchronous Logic Signal Pulses

  • Author

    Catt, Ivor

  • Author_Institution
    Semiconductor Products Division, Motorola Inc., Phoenix, Ariz.
  • Issue
    1
  • fYear
    1966
  • Firstpage
    108
  • Lastpage
    111
  • Abstract
    The gating of asynchronous signals causes logical errors. It is possible to reduce the frequency of these errors, but the price paid is a severe loss of time and extra cost in hardware.
  • Keywords
    Chaos; Clocks; Costs; Frequency synchronization; Hardware; Logic; Metastasis; Sampled data systems;
  • fLanguage
    English
  • Journal_Title
    Electronic Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0367-7508
  • Type

    jour

  • DOI
    10.1109/PGEC.1966.264407
  • Filename
    4038676
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=887557