Simultaneous Multiple Response in Associative Memories and Readout of the Detector Matrix

One of the time-consuming procedures in the operation of a digital computer arises from the need to rearrange portions of words during the execution of certain instructions. In a typical situation, the first stage of a complex control sequence is concerned with the disassembly of the word prior to sending the parts to registers for appropriate arithmetic treatment, and the last stage with reassembly into standard format. This overhead can be wasteful even when the interregister wiring has been chosen with a particular format in mind, and is accentuated whenever a nonstandard format is encountered.