New input/output designs for high speed static CMOS RAM

Author

Akiya, Masahiro ; Ohara, Mamoru

Volume

14

Issue

5

fYear

1979

fDate

10/1/1979 12:00:00 AM

Firstpage

823

Lastpage

828

Abstract

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256×4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 μm layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.

Keywords

Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; CMOS memory circuits; CMOS technology; Circuit stability; Decoding; Driver circuits; Power dissipation; Random access memory; Read-write memory; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1979.1051278

Filename

1051278