DocumentCode
887712
Title
A study in the use of PLA-based macros
Author
Cook, Peter W. ; Ho, Chung W. ; Schuster, Stanley E.
Volume
14
Issue
5
fYear
1979
Firstpage
833
Lastpage
840
Abstract
Describes a study in which a PLA-based macro design of a small processor is carried out in the same technology as the original `random´ logic design of the same processor. The objectives of the study were to determine gains or losses in `technology utilization´ when a PLA-based approach is used to replace the more conventional `random´ logic approach. The results in this case are a design of equal performance and density, with only one-third the power dissipation of the original design.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated logic circuits; Large scale integration; field effect integrated circuits; integrated circuit technology; integrated logic circuits; large scale integration; Combinatorial mathematics; Digital systems; Large scale integration; Logic circuits; Logic design; Logic testing; Microprocessors; Paper technology; Programmable logic arrays; Registers;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1979.1051280
Filename
1051280
Link To Document