Universal FASTBUS Interface Boards and Associated Modules

A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two different but plug compatible boards, one using TTL programmable logic and featuring average latency of 185 nanoseconds and capable of cycle times of 200 nanoseconds, and the other using ECL macrocell arrays and featuring average latency of 35 nanoseconds and capable of cycle times of this order. Use of these boards in both unintelligent and intelligent Fastbus host interfaces as well as self contained Fastbus processing modules is described. This work has been and is being supported by the U. S. Department of Energy under SBIR contracts DE-ACO1-83ER80078, DE-ACO2-85ER80273, and DE-ACO2-87ER80455, and by the New York State Science and Technology Foundation under contract SBIR (86)-58.