• DocumentCode
    888040
  • Title

    Return Path Assumption Validation for Inductance Modeling in Digital Design

  • Author

    David, Lauréline ; Crégut, Corinne ; Huret, Fabrice ; Quéré, Yves ; Nyer, Frédéric

  • Author_Institution
    STMicroelectron., Crolles
  • Volume
    30
  • Issue
    2
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    295
  • Lastpage
    300
  • Abstract
    Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing prelayout effective inductance estimations are suggested.
  • Keywords
    digital integrated circuits; inductance; integrated circuit interconnections; integrated circuit modelling; digital design; inductance modeling; on-chip interconnects; return path assumption validation; return path localization; Circuit noise; Coupling circuits; Delay effects; Delay estimation; Frequency; Inductance; Integrated circuit interconnections; Propagation delay; RLC circuits; Working environment noise; Digital circuit; inductance; interconnection; modeling;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2007.896002
  • Filename
    4214900
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=888040