Title :
Fast parallel algorithms for binary multiplication and their implementation on systolic architectures
Author :
Sinha, Bhabani P. ; Srimani, Pradip K.
Author_Institution :
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
fDate :
3/1/1989 12:00:00 AM
Abstract :
Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two´s complement numbers with constant differences in time
Keywords :
digital arithmetic; parallel algorithms; VLSI implementation; binary multiplication; column compression; n-bit binary numbers; parallel algorithms; systolic architectures; two´s complement numbers; Adders; Binary trees; Chip scale packaging; Computer architecture; Computer science; Integrated circuit interconnections; Iterative algorithms; Parallel algorithms; Parallel processing; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
