• DocumentCode
    888217
  • Title

    Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

  • Author

    Sinha, Bhabani P. ; Srimani, Pradip K.

  • Author_Institution
    Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
  • Volume
    38
  • Issue
    3
  • fYear
    1989
  • fDate
    3/1/1989 12:00:00 AM
  • Firstpage
    424
  • Lastpage
    431
  • Abstract
    Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two´s complement numbers with constant differences in time
  • Keywords
    digital arithmetic; parallel algorithms; VLSI implementation; binary multiplication; column compression; n-bit binary numbers; parallel algorithms; systolic architectures; two´s complement numbers; Adders; Binary trees; Chip scale packaging; Computer architecture; Computer science; Integrated circuit interconnections; Iterative algorithms; Parallel algorithms; Parallel processing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.21128
  • Filename
    21128
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=888217