Realistic fault model for external shorts in MOS technologies

The authors focus on the fault modelling of external shorts in H-, C- and BiC-MOS digital circuits. In the context of functional testing, it is demonstrated that eight different electrical configurations may appear depending on the topological and technological parameters of the fault. Therefore, eight new logical models are defined showing that the wired-OR and wired-AND models, classically used for test pattern generation, fault simulation and defect coverage evaluation are not sufficient.