DocumentCode :
888375
Title :
High Density Integrated Computing Circuitry with Multiple Valued Logic
Author :
Current, K. Wayne
Volume :
15
Issue :
1
fYear :
1980
fDate :
2/1/1980 12:00:00 AM
Firstpage :
127
Lastpage :
131
Abstract :
It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quatemary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case.
Keywords :
Counting circuits; Digital circuits; Logic circuits; Adders; Arithmetic; Combinational circuits; Counting circuits; Digital signal processing; Logic circuits; Logic devices; Multivalued logic; Sequential circuits; Signal processing;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1980.1051345
Filename :
1051345
Link To Document :
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