Solutions to heavy ion induced avalanche burnout in power devices

A review of normal breakdown and current induced avalanche (CIA) breakdown mechanisms in silicon power transistors is presented. The applicability of the CIA model to heavy ion induced burnout is shown, and solutions to CIA in silicon power semiconductors are given. It is noted that solving the problem of CIA burnout in npn bipolar and n-channel DMOS devices is, at best, difficult. Several techniques of hardening these devices to the effects of heavy ion, dose-rate induced failure, and any other condition producing CIA are discussed. The most effective techniques are those that minimize the emitter current injection by reducing the emitter injection efficiency or making the parasitic bipolar more difficult to turn on. However, it is believed that the simplest solution to the problem is to use pnp bipolar and p-channel DMOS devices whenever possible