Title :
Low power SEU immune CMOS memory circuits
Author :
Liu, M. Norley ; Whitaker, Sterling
Author_Institution :
NASA Space Eng. Res. Center for VLSI Syst. Design, Idaho Univ., Moscow, ID, USA
fDate :
12/1/1992 12:00:00 AM
Abstract :
The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition
Keywords :
CMOS integrated circuits; SRAM chips; flip-flops; ion beam effects; logic design; radiation hardening (electronics); CMOS memory circuits; SEU hardened; SRAM; flip-flop design; logic/circuit design technique; low power; space application; static power consumption; CMOS logic circuits; CMOS memory circuits; Circuit synthesis; Clocks; Energy consumption; Integrated circuit reliability; Logic design; NASA; Read-write memory; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
