Study of device parameters for analog IC design in a 1.2 μm CMOS-SOI technology after 10 Mrad [for hadron colliders]

Radiation-hardened SOI-CMOS is a candidate technology for mixed analog-digital signal processing electronics in experiments at future high luminosity hadron colliders. In view of this application, the analog parameters of transistors realized in the Thomson TMS HSO13-HD technology were studied before and after exposure to total doses similar to those expected in the CERN Large Hadron Collider (LHC). The devices were irradiated up to 10 Mrad with ⁶⁰Co and 3×10¹⁴ neutrons/cm². The changes in the threshold voltage V_th of front and back gates, leakage current, and transconductance are studied. Subthreshold slope and charge pumping techniques were used to estimate the interface state formation. Noise measurements in the 0.1-kHz to 3-MHz bandwidth range were performed. The noise is comparable to that of a bulk CMOS process. Postirradiation effects were regularly monitored, and threshold voltage rebound for n-channel transistors was observed