Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5%-40%. A test-chip is designed and fabricated in IBM 0.13-mum CMOS technology to successfully demonstrate the operation of the self-repair system.