Title :
A high-speed ECL 100K compatible 64x4 bit RAM with 6 ns access time
Author :
Ernst, Herbert ; Förtsch, Wolfgang ; Witsch, Helmut V.
fDate :
6/1/1980 12:00:00 AM
Abstract :
An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family.
Keywords :
Bipolar integrated circuits; Integrated memory circuits; Large scale integration; Random-access storage; bipolar integrated circuits; integrated memory circuits; large scale integration; random-access storage; Adaptive arrays; Circuits; Energy consumption; Isolation technology; Logic arrays; Logic devices; Power dissipation; Random access memory; Read-write memory; Resistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1980.1051389
