A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers

Author

Zheng, Hui ; Luong, Howard C.

Author_Institution

Dept. of Electr. & Comput. Eng, Hong Kong Univ. of Sci. & Technol.

Volume

42

Issue

6

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

1250

Lastpage

1260

Abstract

This paper presents the design of a CMOS synthesizer for dual-conversion zero-IF2 Multi-Band OFDM (MB-OFDM) transceivers covering the first 9 frequency bands from 3.1GHz to 8.0GHz, each with a bandwidth of 528 MHz. A wideband single-sideband mixer with wideband inductive network loading is proposed. Moreover, a modified transformer-coupled quadrature VCO and interconnection-loading-insensitive layout technique are employed. Fabricated in TSMC 0.18-mum CMOS process and operated at 1.5V, the synthesizer measures phase noise of -127.4dBc/Hz at 10MHz offset, integrated phase noise of 4.43deg, sideband suppression of better than -22 dBc, and a switching time of less than 1ns while consuming 59 mA

Keywords

CMOS analogue integrated circuits; OFDM modulation; field effect MIMIC; frequency synthesizers; mixers (circuits); transceivers; ultra wideband communication; 0.18 micron; 1.5 V; 3.1 to 8 GHz; 528 MHz; 59 mA; CMOS synthesizer; LO generation; OFDM UWB transceivers; TSMC CMOS process; interconnection-loading-insensitive layout; multi-band OFDM transceivers; phase-locked loop; single-sideband mixer; transformer-coupled quadrature VCO; wideband inductive network loading; Bandwidth; CMOS process; Frequency synthesizers; Noise measurement; OFDM; Phase measurement; Phase noise; Transceivers; Voltage-controlled oscillators; Wideband; LO generation; MB-OFDM; PLL; QVCO; UWB; VCO; phase-locked loop; synthesizer; ultra-wideband; wideband loading;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.897135

Filename

4214989