Abstract :
A new logic simulator is described which uses the output from a mask analysis program as the input circuit data. Each circuit node is treated as the output of a multiinput transfer gate. Three logical states: 0, 1, and X, and four auxiliary states: D, S, B, and Z, are used in the simulation with a unit gate delay. The circuit node in the E/D MOS LSI is sorted into two types. The one, named TG, looks like the output of a multiinput transfer gate, and the other, named PTG, is like a transfer gate with a pulling-up transistor. MACLOS was successfully applied to a 12-bit microprocessor chip including 10K transistors and a RAM block fabricated by the E/D MOS process. It took 25 min for ACOS 700 to simulate the microprocessor for 213 clock cycles; 49K words of core memory were used in the simulation.
Keywords :
Digital simulation; Field effect integrated circuits; Integrated logic circuits; Large scale integration; Masks; digital simulation; field effect integrated circuits; integrated logic circuits; large scale integration; masks; Analytical models; Circuit simulation; Clocks; Delay; Large scale integration; Logic circuits; MOSFETs; Microprocessor chips; Random access memory; Read-write memory;
