Title :
A 1-/spl mu/m Mo-Poly 64-Kbit MOS RAM
Author :
Yanagawa, Fumihiko ; Kiuchi, Kazuhide ; Hosoya, Tetsuo ; Tsuchiya, Toshiaki ; Amazawa, Takao ; Mano, Tsuneo
Abstract :
This paper describes a 1-m 64-kbit MOS RAM using Mo-poly technology. New 1-/spl mu/ m double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-/spl mu/ m Si-gate FET´s in peripheral circuitry. A 1-/spl mu/ m Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1/spl mu/ m process technologies. The cell size and die size were 8 /spl mu/ m X 8 /spl mu/ m and 3 mm X 3 mm, respectively. Access time was less than 100 ns.
Keywords :
Elemental semiconductors; Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Molybdenum; Random-access storage; Silicon; Aluminum; Annealing; Circuits; Electrodes; FETs; Nitrogen; Oxidation; Propagation delay; Read-write memory; Sheet materials;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1980.1051453
