Title :
A Dense Gate Matrix Layout Method for MOS VLSI
Author :
Lopez, Alexander D. ; Law, Hung-Fai S.
Abstract :
A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.
Keywords :
Circuit layout CAD; Field effect integrated circuits; Large scale integration; Circuit topology; Computational geometry; Conductors; Costs; Design automation; Integrated circuit interconnections; Logic design; Silicon; Very large scale integration; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1980.1051462
