Title :
A 100 ns 5 V only 64Kx1 MOS dynamic RAM
Author :
Chan, John Y. ; Barnes, John J. ; Wang, Chen Y. ; De Blasi, Janet M. ; Guidry, Mark R.
Abstract :
A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL negative undershoot protection on address circuits, and 7) active hold-down transistors for both X and Y drivers. A nominal 100 ns access time and power dissipation of less than 150 mW was observed during active operation with a 20 mW power dissipation in the standby mode.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Alpha particles; Capacitance; Capacitors; Circuit synthesis; DRAM chips; Dry etching; Inverters; Power supplies; Protection; Signal design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1980.1051480
