Title :
A 5 V-only 64K dynamic RAM based on high S/N design
Author :
Masuda, Hiroo ; Hori, Ryoichi ; Kamigaki, Yoshiaki ; Itoh, Kiyoo ; Kawamoto, Hiroshi ; Katto, Hisao
Abstract :
A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule. The design features of this dynamic RAM are described. In particular, memory cell and S/N (signal/noise) designs are focused of a dynamic RAM with an on-chip bias generator. The device fabricated provides a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Capacitance; Circuit noise; DRAM chips; Dynamic voltage scaling; Flip-flops; Power supplies; Random access memory; Read-write memory; Signal design; Substrate hot electron injection;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1980.1051481
