DocumentCode
889853
Title
On the optimal design of multiple-valued PLAs
Author
Sasao, Tsutomu
Author_Institution
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
Volume
38
Issue
4
fYear
1989
fDate
4/1/1989 12:00:00 AM
Firstpage
582
Lastpage
592
Abstract
A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit decoders and a permutation network on the input. Using the number of columns required to realize a given function as a measure to compare PLAs, it is shown that type 3 PLAs are superior to type 2, which in turn are superior to type 1
Keywords
logic arrays; logic design; many-valued logics; 2-bit decoders; literal functions; multiple-valued PLAs; optimal design; permutation network; programmable logic arrays; Circuit testing; Costs; Decoding; Encoding; Integrated circuit interconnections; Logic circuits; Logic design; Programmable logic arrays; Signal generators; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.21150
Filename
21150
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