DocumentCode
889901
Title
Highly reliable testing of ULSI memories with on-chip voltage-down converters
Author
Tsukude, Masaki ; Arimoto, Kazutami ; Hidaka, Hideto ; Konishi, Yasuhiro ; Hayashikoshi, Masanori ; Suma, Katsuhiro ; Fujishima, Kazuyasu
Author_Institution
Mitsubishi Electr. Corp., Hyogo, Japan
Volume
10
Issue
2
fYear
1993
fDate
6/1/1993 12:00:00 AM
Firstpage
6
Lastpage
12
Abstract
Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V/sub CC/ levels during the water sort test (WT) and the final shipping test (FT).<>
Keywords
VLSI; integrated circuit testing; integrated memory circuits; power convertors; ULSI memories; VDC tuning technique; final shipping test; on-chip voltage-down converters; testing techniques; water sort test; Circuit optimization; Circuit testing; Differential amplifiers; Feedback; Fluctuations; Fuses; Stress; Threshold voltage; Tunable circuits and devices; Ultra large scale integration;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.211523
Filename
211523
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