Title :
Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing
Author :
Naik, Samlr ; Agricola, Frank ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and I/sub DDQ/ testing is presented. The key to the method is the development of a defect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memory manufacturing process.<>
Keywords :
CMOS integrated circuits; SRAM chips; failure analysis; integrated circuit testing; I/sub DDQ/ testing; defect modeling; defect-to-signature vocabulary; failure analysis method; high-density CMOS SRAMs; inductive fault analysis; multimegabit-memory manufacturing process; static RAMs; CMOS process; Fabrication; Failure analysis; Fault diagnosis; Manufacturing processes; Random access memory; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor device testing; Semiconductor devices;
Journal_Title :
Design & Test of Computers, IEEE
