DocumentCode
889966
Title
A tutorial on built-in self-test. 2. Applications
Author
Agrawal, Vishwani D. ; Kime, Charles R. ; Saluja, Kewal K.
Author_Institution
AT&T Bell Lab., Murray Hill, NJ, USA
Volume
10
Issue
2
fYear
1993
fDate
6/1/1993 12:00:00 AM
Firstpage
69
Lastpage
77
Abstract
For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.<>
Keywords
built-in self test; integrated memory circuits; logic arrays; logic testing; random-access storage; read-only storage; BIST techniques; PLAs; RAMs; ROMs; built-in self-test; hardware structures; pattern generation; response analysis; structured logic; Automatic testing; Built-in self-test; Circuit testing; Clocks; Hardware; Logic testing; Read only memory; Shift registers; Test pattern generators; Tutorial;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.211530
Filename
211530
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