A precision autozeroing sample and hold integrated circuit

A precision sample and hold integrated circuit with autozeroing of all DC errors is described. Experimental data have shown that it provides the accuracy necessary for use in 12 bit data acquisition systems. Application of noise-optimized silicon gate FET devices for the input circuitry of amplifiers which buffer the hold capacitor results in a low droop rate and allows the sample/hold to operate without external components. Common mode rejection is optimized through implementation of a modified current source offering extremely high output impedance at high operating currents. The device includes all digital control and switching circuitry.