Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test

Author

Ker, Ming-Dou ; Hsu, Sheng-Fu

Author_Institution

Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu

Volume

48

Issue

1

fYear

2006

Firstpage

161

Lastpage

171

Abstract

Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-mum CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products

Keywords

CMOS integrated circuits; electrostatic discharge; filters; integrated circuit noise; integrated circuit testing; rectifiers; 0.25 mum; CMOS IC; board-level noise filter networks; electrostatic discharge; ring oscillator circuit; silicon-controlled rectifier; system-level ESD test; transient-induced latchup; CMOS technology; Chip scale packaging; Circuit testing; Electrostatic discharge; Filters; Integrated circuit technology; Rectifiers; Ring oscillators; System testing; Thyristors; Board-level noise filter; SCR; latchup; system-level ESD test; transient-induced latchup (TLU);

fLanguage

English

Journal_Title

Electromagnetic Compatibility, IEEE Transactions on

Publisher

ieee

ISSN

0018-9375

Type

jour

DOI

10.1109/TEMC.2006.870681

Filename

1614049