• DocumentCode
    890318
  • Title

    MOSFET threshold extraction circuit

  • Author

    Manaresi, N. ; Franchi, E. ; Gnudi, A. ; Baccarani, G.

  • Author_Institution
    Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
  • Volume
    31
  • Issue
    17
  • fYear
    1995
  • fDate
    8/17/1995 12:00:00 AM
  • Firstpage
    1434
  • Lastpage
    1435
  • Abstract
    A novel method of the extraction of MOST threshold voltage (VT) is presented. It is based on a self-biasing loop and it allows an output voltage equal to the VT of either n-MOS or p-MOS transistors to be obtained without any restriction on the particular type of well
  • Keywords
    CMOS analogue integrated circuits; analogue processing circuits; MOST threshold voltage; NMOSFET; PMOSFET; n-MOS transistors; p-MOS transistors; self-biasing loop; threshold extraction circuit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950990
  • Filename
    464161
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=890318