Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggressively scaled dense structures. The focus is on nested transistors, which is a technologically very important structure that consists of a chain of gates on one active area. It will be shown that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations, which accordingly leads to different scaling guidelines to obtain a layout-insensitive strained CESL technology. Decreasing the CESL thickness is not enough for technology scaling; also, adapting the spacer dimensions is indispensable to scale a strained CESL technology from one technology node to the next.