DocumentCode
890536
Title
A Parallel Accumulator for a General-Purpose Computer
Author
Quatse, Jesse T. ; Keir, Roy A.
Author_Institution
Computation Center, Carnegie Institute of Technology, Pittsburgh, Pa.
Issue
2
fYear
1967
fDate
4/1/1967 12:00:00 AM
Firstpage
165
Lastpage
171
Abstract
A family of parallel synchronous comparitors and adders are described which can be constructed entirely of either NOR or NAND circuits. An adder is shown combined with registers to form a high speed but inexpensive 20-bit accumulator. The standard accumulator functions of ADD, UNITE, EXTRACT, LEFT SHIFT, and RIGHT SHIFT are obtained at the cost of 7.5 gates per bit and 12 gate delays for stable sum.
Keywords
Adders; Arithmetic; Bismuth; Concurrent computing; Cost function; Delay; Logic circuits; Registers; Sequential circuits; Signal design; Accelerated carry; accumulator; adder; arithmetic unit; carry logic;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1967.264812
Filename
4039024
Link To Document