DocumentCode
890647
Title
A 5-bit building block for 20 MHz A/D converters
Author
Fiedler, Horst L. ; Hoefflinger, Bernd ; Demmer, Walter ; Draheim, Peter
Volume
16
Issue
3
fYear
1981
fDate
6/1/1981 12:00:00 AM
Firstpage
151
Lastpage
155
Abstract
Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.
Keywords
Analogue-digital conversion; Field effect integrated circuits; Integrated logic circuits; analogue-digital conversion; field effect integrated circuits; integrated logic circuits; Circuit synthesis; Data conversion; Electrons; Error correction; Latches; Logic; MOS devices; Physics; Quantization; Solid state circuits;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1981.1051565
Filename
1051565
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