A CMOS pipelined single channel digital echo canceller

Recent advances in LSI/VLSI have made the integration of digital echo cancellers both feasible and economical. The design presented features a universal CMOS ALU which is capable of direct I/O with /spl mu/-law encoded data. The ALU is pipelined to achieve high processing speed with low power dissipation. Based on this /spl mu/-law ALU, a 128-tap CMOS pipelined single channel digital echo canceller was designed and simulated, and a prototype was built. Experimental results for a 4 kHz sampling rate are presented.