DocumentCode :
891149
Title :
HMOS-CMOS-a low-power high-performance technology
Author :
Yu, Ken ; Chwang, Ronald J C ; Bohr, Mark T. ; Warkentin, Paul A. ; Stern, Seth ; Berglund, C. Neil
Volume :
16
Issue :
5
fYear :
1981
fDate :
10/1/1981 12:00:00 AM
Firstpage :
454
Lastpage :
459
Abstract :
HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-μm channel length and 400-Å gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single poly technology suitable for microprocessor and static RAM applications. A 4K static RAM test vehicle is described featuring fully CMOS six-transistor memory cell, a chip size of 19600 mil/SUP 2/, 75 μW standby power, data retention down to a V/SUB cc/ voltage of 1.5 V and a minimum chip select and address access time of 25 ns.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Boron; CMOS technology; Conductivity; Delay; Doping; Fabrication; Implants; MOS devices; Virtual manufacturing; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1981.1051622
Filename :
1051622
Link To Document :
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