A Realization Algorithm Using Three-Input Majority Elements

A modification of Akers´ method of realizing Boolean functions with three-input majority gates is presented. One of the fundamental parts in Akers´ procedure is the construction of a logically passive self-dual, or LPSD. This paper presents a more precise construction of the LPSD. In addition, a procedure is described to adapt the method to minimization of the number of delay elements. A delay element table is introduced to aid in the selection of majority gates. A second factor in reducing delay elements is limiting the number of levels of logic in the realization. Examples illustrate the substantial reduction in delay elements when these methods are employed.