A 20 ns, low power, NMOS 1Kx4 static RAM

Using scaled NMOS processing and novel circuit design techniques to enhance the speed-power product, a high-speed, low power, fully static 1024-word/spl times/4-bit random access memory has been developed. Applications related requirements such as fast chip select access time and /spl times/4 organization for cache and microcode store memories are central to the device definition. Highly producible 4.5 /spl mu/m design rules with 2.5 /spl mu/m polysilicon gate lengths are incorporated in addition to depletion load transistors in the memory array. The resulting TTL-compatible, 5 V only 1K/spl times/4 static RAM achieves a typical address access time of 20 ns and a chip select access time of 5 ns with power dissipation under 350 mW.